A fast-rising demand for always-on intelligent and connected energy-autonomous integrated systems is stemming from the convergence of the Internet of Things (IoT) and Artificial Intelligence (AI), involving verticals including Industry 4.0, distributed sensing for smart buildings/cities, mobility/connectivity, wearables. Such embedded systems continuously monitor sensor signals, detect the occurrence of events, make sense of them through on-chip data analytics, and wirelessly provide the cloud with fine-grain big data for large-scale event comprehension. In such applications, the stringent requirements of ultra-low standby/active power, high peak performance, low manufacturing cost and design effort are not well supported by other commercially available fabrication technologies, which entail either cutting edge density at larger manufacturing and design cost (e.g., many tens to hundreds of M$ per chip), or lower-cost and less advanced bulk CMOS techologies (large standby power, not as high performance or high density).

The Fully-Depleted Silicon on Insulator FDSOI technology fits such requirements, in view of its ability to tune the transistor threshold voltage via dynamic back biasing (BB), which enables ample scaling of standby and average power, performance, voltage, and desirable device characteristics for energy-efficient wireless communications. Its planar nature makes it highly cost-effective. Although FDSOI manufacturing is now well-established, the exploitation of back biasing in commercial chips has been mostly limited to static tuning, design-specific and proprietary techniques, due to the lack of a comprehensive design ecosystem, reusable building blocks from standard cells to macros for automated system integration (IP), design methodologies, and industry-proven solutions. Such gap at the design stage of the FDSOI value chain has restricted the potential design economy of scale and design cost reductions.

FD-fAbrICS tackles the above challenges through the collaboration of NUS, the Singapore’s flagship university, with world industry leaders Soitec, NXP and Dolphin Design in FDSOI manufacturing and design. The grand goal is to unlock the full potential of FDSOI via the research investigation and the silicon demonstration of innovative design methods with unprecedented capabilities:

1) innovative drop-in design IP for dynamic back biasing and wide supply adaptation in digital sub-systems with 10-100X lower power than state of the art (from foundational IP to high-level IP for AI/IoT)

2) novel methodologies for in-situ push-button design based on standard cells, suppressing separate/customized blocks for BB, reducing the design/cost barrier by 5-10X (becoming equivalent to conventional bulk CMOS), shortening the design cycle by >2X

3) innovative circuits for highly-linear highly-efficient radios for wireless communications (e.g., WiFi6)

4) compelling demonstrators made available as prototypes and baseline for further customization for next-generation systems: a) general-purpose ultra-low power IoT chip platform (0.2mW), b) general-purpose neuromorphic accelerator demonstrated in auditive cognition with >10X lower power than the state of the art (“Siri/Alexa anywhere”).

The above advances will enable new FDSOI design capabilities, and fast ramp-up of a new breed of high added value intelligent & connected systems (AI/IoT). To this aim, an FDSOI design ecosystem (design IP and automated methodologies) and an Industry Consortium will be created for proliferation and fruition through the semiconductor value chain. As ultimate outcome, FD-FAbrICS aims to position Singapore as worldwide design hub for FDSOI always-on intelligent/connected integrated systems, generating core knowledge to support the strong global demand for AI/IoT systems.